ULK 这段话在说什么?
时间:2010-07-30
来源:互联网
本帖最后由 zylthinking 于 2010-07-30 11:24 编辑
The content of the first entries of the Page Global Directory that map linear addresses lower than 0xc0000000 (the first 768 entries with PAE disabled, or the first 3 entries with PAE enabled) depends on the specific process. Conversely, the remaining entries should be the same for all processes and equal to the corresponding entries of the master kernel Page Global Directory (see the following section).
似乎是说, 线性地址前部分(0-3G) 各个应用不同, 最后1G相同, 但标红的文字是什么意思, 我在前面看到的相同的数字是 linux kernel 存放在物理地址 3MB 以内, 但这个和它似乎没有关系: 至少我看着是在说线性地址的 低3M.
整体看起来, 简直不知所云。
The content of the first entries of the Page Global Directory that map linear addresses lower than 0xc0000000 (the first 768 entries with PAE disabled, or the first 3 entries with PAE enabled) depends on the specific process. Conversely, the remaining entries should be the same for all processes and equal to the corresponding entries of the master kernel Page Global Directory (see the following section).
似乎是说, 线性地址前部分(0-3G) 各个应用不同, 最后1G相同, 但标红的文字是什么意思, 我在前面看到的相同的数字是 linux kernel 存放在物理地址 3MB 以内, 但这个和它似乎没有关系: 至少我看着是在说线性地址的 低3M.
整体看起来, 简直不知所云。
作者: zylthinking 发布时间: 2010-07-30
回复 zylthinking
启用PAE后,虚拟地址转换的也目录项变为PDPT,包含4项了。
启用PAE后,虚拟地址转换的也目录项变为PDPT,包含4项了。
QUOTE:
2.4.5. The Physical Address Extension (PAE) Paging Mechanism
QUOTE:
Intel has satisfied these requests by increasing the number of address pins on its processors from 32 to 36. Starting with the Pentium Pro, all Intel processors are now able to address up to 236 = 64 GB of RAM. However, the increased range of physical addresses can be exploited only by introducing a new paging mechanism that translates 32-bit linear addresses into 36-bit physical ones.
QUOTE:
A new level of Page Table called the Page Directory Pointer Table (PDPT) consisting of four 64-bit entries has been introduced.
作者: kgn28 发布时间: 2010-07-30
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